Intel announces 32-layer 3D NAND chips, plans for larger-than-10TB SSDs

      

It’s been clear for several years that three-dimensional NAND die stacking, in which chip layers are oriented vertically as opposed to horizontal planar structures was the way forward for next-generation chip designs. Until now, Samsung has been the only company to take that plunge, but that’s going to change in 2015 with the launch of Intel’s own solution in 2015.
According to Intel, its 256-gigabit MLC NAND chips will consist of 32 layers, and will also be available in a 384-gigabit TLC configuration. Intel is claiming that its own 256Gb die sets efficiency records, but as Anandtech reports, this depends on how you count — Samsung has consciously chosen to use a 32-layer 86Gbit die to minimize its die foot print, as opposed to maximizing capacity. This gives Samsung’s V-NAND the smallest die size of any product currently on the market, with size being a very important factor in many markets.

Moving back up the nanometer ladder

Intel, like Samsung, is expected to announce that it uses a much larger process node for its 3D NAND. In Samsung’s case, it uses a 40nm process for 3D NAND, despite the fact that its working on 14nm planar technology for both logic and DRAM devices. Intel and Micron have already launched 16nm 2D NAND, but the fundamental characteristics of flash mean that device reliability decreases as process nodes shrink.